Loihi 2 packs 1 million neurons in a chip half the size of its predecessor.
Category: computing – Page 177
As the company’s first tile-based CPU based on its new Intel 4 process, this is an entirely different CPU from everything that has come before it.
Shirriff’s blog goes into a deep dive with a look inside the HP PHI chip, its construction, and die. He even examines its logic gates, first-in-first-out buffers (FIFOs), and address decoder. Please check out the blog for all these finer details and more.
In conclusion, the computer historian echoes our initial thoughts that this silicon-on-sapphire IC is “interesting as an example of a ‘technology of the future’ that didn’t quite pan out.”
Shirriff also contrasts late 70s era processors built on silicon-on-sapphire vs regular silicon in terms of energy consumption and clock speeds. Would you be surprised to hear that silicon-on-sapphire ICs were far superior using these metrics? Things might have panned out differently if these transparent ICs had been mass-produced at better yields and lower manufacturing costs. A frightening statistic highlighted by Shirriff is that HP’s silicon-on-sapphire yields were a mere 9%.
The researchers embedded this prototype in a biodegradable, chip-like implant that combined energy harvesting and energy storage. When the prototype was attached to a medical implant, power passed through the circuit directly to the device and into the capacitor to ensure a constant power supply.
In rats, the wireless implant worked for up to 10 days and dissolved completely within two months — proving its biodegradability. But it could potentially last longer if the team thickened the protective polymer and wax layers encasing the system, Lan said.
The researchers also tested the wireless charger as a drug-delivery system and delivered anti-inflammatory medicine to rats with a fever. After 12 hours, the rats that had no implants had much higher body temperatures than those with the chips, suggesting the device was successfully delivering the medicine.
Thanks in part to Elon Musk, the field of brain-computer interfaces has captured both public and investor interest, with a cadre of companies now developing implantable devices.
Major technical improvements to a quantum computer based on trapped ions could bring a large-scale version closer to reality.
Scientists are exploring various platforms for future large-scale quantum computation. Among the leading contenders, those in which the quantum bits (qubits) are trapped ions stand out for their low-error operation. However, scaling up such platforms to the millions of qubits needed for utility-scale quantum computing is a daunting task. Now Steven Moses at Quantinuum in Colorado and colleagues describe an impressive new trapped-ion quantum computer, the Quantinuum System Model H2, in which they have been able to increase the number of qubits (from 20 to 32) without increasing the error rate [1]. The researchers have put this system through its paces with full component-level testing, a suite of industry-standard benchmark tests, and a set of diverse applications.
In a typical trapped-ion quantum computer, a linear chain of ions is confined by an electric potential using direct-current (dc) and radio-frequency (rf) fields. Whereas the ion-trap apparatus can be at any temperature, the ions themselves need to be laser cooled to near their ground state. Their motion can then be quantized, and the resulting motional modes can be used to entangle any pair of ions in the chain—a requirement for performing quantum operations. However, controlling individual ions in a long chain comes with its own technical difficulties, and it is unlikely that a million qubits—as needed to build a universal, fault-tolerant quantum computer [2]—could be trapped in a single potential.
Computer-generated holography (CGH) represents a cutting-edge technology that employs computer algorithms to dynamically reconstruct virtual objects. This technology has found extensive applications across diverse fields such as three-dimensional display, optical information storage and processing, entertainment, and encryption.
Despite the broad application spectrum of CGH, contemporary techniques predominantly rely on projection devices like spatial light modulators (SLMs) and digital micromirror devices (DMDs). These devices inherently face limitations in display capabilities, often resulting in narrow field-of-view and multilevel diffraction in projected images.
In recent developments, metasurfaces composed of an array of subwavelength nanostructures have demonstrated exceptional capabilities in modulating electromagnetic waves. By introducing abrupt changes to fundamental wave properties like amplitude and phase through nanostructuring at subwavelength scales, metasurfaces enable modulation effects that are challenging to achieve with traditional devices.
Over the past few years, engineers have been trying to devise alternative hardware designs that would allow a single device to both perform computations and store data. These emerging electronics, known as computing-in-memory devices, could have numerous advantages, including faster speeds and enhanced data analysis capabilities.
To store data safely and retain a low power consumption, these devices should be based on ferroelectric materials with advantageous properties and that can be scaled down in terms of thickness. Two-dimensional (2D) semiconductors that exhibit a property known as sliding ferroelectricity have been found to be promising candidates for realizing computing-in-memory, yet attaining the necessary switchable electric polarization in these materials can prove difficult.
Researchers at National Taiwan Normal University, Taiwan Semiconductor Research Institute, National Yang Ming Chiao Tung University and National Cheng Kung University recently devised an effective strategy to achieve a switchable electric polarization in molybdenum disulfide (MoS2). Using this method, outlined in a Nature Electronics paper, they ultimately developed new promising ferroelectric transistors for computing-in-memory applications.
We report the experimental realization and room-temperature operation of a low-power (20 pW) moiré synaptic transistor based on an asymmetric bilayer graphene/hexagonal boron nitride moiré heterostructure.