The semiconductor industry’s long held imperative—Moore’s Law, which dictates that transistor densities on a chip should double roughly every two years—is getting more and more difficult to maintain. The ability to shrink down transistors, and the interconnects between them, is hitting some basic physical limitations. In particular, when copper interconnects are scaled down, their resistivity skyrockets, which decreases how much information they can carry and increases their energy draw.
The industry has been looking for alternative interconnect materials to prolong the march of Moore’s Law a bit longer. Graphene is a very attractive optionin many ways: The sheet-thin carbon material offers excellent electrical and thermal conductivity, and is stronger than diamond.
However, researchers have struggled to incorporate graphene into mainstream computing applications for two main reasons. First, depositing graphene requires high temperatures that are incompatible with traditional CMOS manufacturing. And second, the charge carrier density of undoped, macroscopic graphene sheets is relatively low.
Making smaller transistors, and the interconnections between them, is getting near impossible. Copper interconnects get more resistive as they are scaled down, making them worse and slower at carrying information. Startup Destination 2D thinks graphene is the solution. They have a novel technique of growing graphene that is CMOS compatible, promising 100x current density improvement over copper.
