Scaling has long been recognized as a major hurdle for quantum processors, along with a need for advances in quantum error correction and the control of quantum gates.
However, while rapid progress has been made in the latter two, far less progress has been made in the development of a CMOS-based scalable system, where the devices and qubits are sufficiently identical that the number of external control signals increases slowly with the number of qubits.
Therefore the development, and taping-out, of a CMOS-based scaling architecture has taken on new significance, as scaling has become the most critical remaining task for building a commercially viable quantum computer.
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