An international team of researchers from the National Physical Laboratory (NPL), IBM, the University of Edinburgh and Auburn University have shown that a new device concept — a ‘squishy’ transistor — can overcome the predicted power bottleneck caused by CMOS (complementary metal-oxide-semiconductor) technology reaching its fundamental limits.
Moore’s law predicted that the number of transistors able to fit on a given die area would double every two years. As transistor density doubled, chip size shrank and processing speeds increased. This march of progress led to rapid advances in information technology and a surge in the number of interconnected devices. The challenge with making anything smaller is that there are fundamental physical limits that can’t be ignored and we are now entering the final years of CMOS transistor shrinkage.
Furthermore, this proliferation is driving an increase in data volume, accompanied by rising demands on energy to process, store and communicate it all; as a result, IT infrastructure now draws an estimated 10 % of the world’s electrical power. Previous efforts have focused on remediation by reducing the amount of energy per bit. However, soon we will hit a power barrier that will prevent continued voltage scaling. The development of novel, low-power devices based on different physical principles is therefore crucial to the continued evolution of IT.
