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To enhance this efficiency, there is a requirement to fabricate electrodes with a porous structure. Unfortunately, existing technologies face challenges in achieving a uniform coating of ceramic materials within electrodes possessing intricate porous structures.

A collaborative research team, comprising Professor Jihwan An and Ph.D. candidate Sung Eun Jo from the Department of Mechanical Engineering at Pohang University of Science and Technology (POSTECH), and others, has successfully produced porous electrodes for SOFCs using latest semiconductor processes. This research has been featured as a back cover article in Small Methods.

The process of atomic layer deposition (ALD) involves depositing gaseous materials onto a substrate surface in thin, uniform atomic layers. In a recent study, Professor Jihwan An’s team, known for their prior work in enhancing the efficiency of SOFCs using ALD, developed and applied a powder ALD process and equipment. This enabled them to precisely coat nano-thin films on fine powders.

A research team, led by Professor Joonki Suh in the Department of Materials Science and Engineering and the Graduate School of Semiconductor Materials and Devices Engineering at UNIST, has made a significant breakthrough in thin film deposition technology. By employing an innovative atomic layer deposition (ALD) process, Professor Seo successfully achieved regular arrangement of tellurium (Te) atoms at low temperatures as low as 50 degrees Celsius.

The ALD method is a cutting-edge thin film process that enables precise stacking of semiconductor materials at the atomic layer level on three-dimensional structures—even at low process temperatures. However, traditional application to next-generation semiconductors requires high processing temperatures above 250 degrees Celsius and additional heat treatment exceeding 450 degrees Celsius.

In this research, the UNIST team applied ALD to monoelemental van der Waals tellurium—a material under extensive investigation for its potential applications in electronic devices and thermoelectric materials.

A research team led by Prof. Kwon Hyuk-jun of the DGIST Department of Electrical Engineering and Computer Science has developed a next-generation AI semiconductor technology that mimics the human brain’s efficiency in AI and neuromorphic systems.

Combinatorial optimization problems (COPs) have applications in many different fields such as logistics, supply chain management, machine learning, material design and drug discovery, among others, for finding the optimal solution to complex problems. These problems are usually very computationally intensive using classical computers and thus solving COPs using quantum computers has attracted significant attention from both academia and industry.

Over the past decade, organic luminescent materials have been recognized by academia and industry alike as promising components for light, flexible and versatile optoelectronic devices such as OLED displays. However, it is a challenge to find suitably efficient materials.

To address this challenge, a joint research team has developed a novel approach combining a machine learning model with quantum-classical computational molecular design to accelerate the discovery of efficient OLED emitters. This research was published May 17 in Intelligent Computing.

The optimal OLED emitter discovered by the authors using this “hybrid quantum-classical procedure” is a deuterated derivative of Alq₃ and is both extremely efficient at emitting light and synthesizable.

A new fabrication process for helical metal nanoparticles provides a simpler, cheaper way to rapidly produce a material essential for biomedical and optical devices, according to a study by University of Michigan researchers.

A research team from City University of Hong Kong (CityU) recently successfully achieved lattice-mismatch-free construction of III-V/chalcogenide core-shell heterostructure nanowires for electronic and optoelectronic applications. This breakthrough addresses crucial technological challenges related to the lattice mismatch problem in the growth of high-quality heterostructure semiconductors, leading to enhanced carrier transport and photoelectric properties.

Nanoscale transistors are in demand for efficient digital circuits, and biasing of each device is critical. These stringent biasing conditions can be relaxed by obtaining precise values of the threshold voltages of the transistor. This leads to more tolerant logic states to the electrical noise.

To meet the requirements of reduced power consumption, CMOS field-effect transistors (FETs) are fabricated such that they operate in enhancement (E) mode, i.e., there are no free charge carriers in the channel at zero gate voltage. On the other hand, depletion (D) mode transistors have higher currents than enhancement mode due to ample charge carrier density.

In contrast to switching applications of FET, for high-frequency applications, off-state of FET is not a compulsory requirement. In fact, the presence of a channel at zero gate bias is advantageous to obtain high transconductance at lower voltages. For Si FETs, the enhancement or depletion modes were determined at the fabrication step of ion implantation doping. However, it is challenging to implement this solution for the new generation of thin materials like organic semiconductors and 2D materials.

Byreddy, O, and Choi have improved detector capabilities for compact, in-hand millimetre wave imaging devices.

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DOI: https://bit.ly/3P0oRmJ